1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to fabricating, by the deep-sub-quarter CMOS process, an ESD protection circuit with low junction capacitance, low leakage current and high ESD protection.
2. Description of the Prior Art
Electrostatic discharge (ESD) occurs when a relatively large amount of voltage or charge generated by rubbing different materials is discharged in a pulse lasting from several to hundreds of nano-seconds depending on the discharge model. Component-level ESD stress on IC products is classified into three models: the human-body model (HBM), the machine-model (MM) and the charged-device model (CDM). To achieve an ESD protection device with reasonable ESD robustness (typically ±2 kV in the HBM ESD stress, ±200V in the MM ESD stress, and ±1000V in the CDM ESD stress) and compliant with general industrial specifications, several methods are proposed to enhance the ESD protection in of the IC products.
The elements that initially encounter an ESD pulse in an integrated circuit are typically input/output (I/O) buffers. The I/O buffers are directly connected to a chip bond pads or terminals thereon which are exposed to the external environment, as shown in FIG. 1. When an ESD pulse is applied to the I/O pad, a large ESD current (several amperes) is discharged through some current paths in the IC. The large ESD current may damage the gate oxide or cause current crowding around the weakest channel surface of the drain side, causing portions of the MOSFET device to burn out, if proper ESD protection circuits are not properly provided in the IC.
Achieving a high level of ESD protection in IC products fabricated by the sub-quarter-micron CMOS process is challenging as the diffusion junction depth is reduced, and the LDD structure and silicidation are generally employed therein. Therefore, it is necessary to integrate ESD protection circuits and devices on the chip to protect the internal circuits from ESD damage. The MOSFET devices shown in FIG. 1 are used as ESD clamp devices to discharge ESD current, and ESD protection capability thereof is dependent upon the level of ESD robustness provided by the clamp devices.
In sub-quarter-micron CMOS technology, the NMOS is fabricated with an LDD structure to overcome the hot-carrier issue. The drain contact to poly spacing (SDG) of the NMOS is achieved by an additional silicide-blocking mask (RPO), which removes CoSi2 silicide at both source and drain regions, providing ESD protection. The LDD structure, however, often degrades ESD robustness. To improve ESD robustness, one additional ESD implantation mask is used in some CMOS processes to eliminate the LDD peak structure. There are several U.S. patents disclosing device structures modified by the ESD implantation for improving ESD robustness.
There are generally two types of ESD implantation, N-type and P-type, as shown in FIGS. 2 and 3, respectively. A typical process flow of N-type arsenic ESD implantation is shown in FIG. 4. Subsequent to implantation of the LDD structure, sidewall spacers are formed on all the devices including the ESD protection devices and internal devices. After source/drain implantation, the ESD protection devices are patterned by the ESD mask so that the sidewall spacers are removed therefrom. The resulting, N-type ion implantation region covers the entire source/drain region and envelops the LDD peak structure in the ESD protection devices. Further, in U.S. Pat. No. 5,672,527, Lee discloses a similar N-type ESD implantation method, wherein the ESD protection devices are formed before the sidewall spacers. The entire source/drain region and the LDD structure of the ESD protection devices are covered by the ESD implantation region but the sidewall spacers are not removed. However, these ESD protection devices suffer an increased breakdown voltage.
In U.S. Pat. No. 5,559,352, Hsue discloses a method of forming an ESD protection device, including a high-energy and heavy P-type ESD implantation step wherein the ions are injected into the substrate through contact openings of the source and drain. The formed ESD implantation regions are located under the source/drain regions, which reduces the source/drain to P-substrate junction breakdown voltage. Therefore, the ESD protection device can be turned on quickly to protect the thin gate oxide of the internal circuit from ESD damage.
In U.S. Pat. No. 5,953,601, Shiue discloses a method of forming an ESD protection device wherein a deeply doped region of opposite conductivity (P-type for NMOS) is formed under the center of the source and drain of the ESD protection device before silicidation. This device structure is similar to Hsue's but additionally avoids silicide degradation and increase of contact resistance, which results from the transportation of metal ions into the depleted region of the junction during the high-energy ESD implantation.
In U.S. Pat. No. 6,114,226, Chang discloses a method of forming an ESD protection device including steps of covering the internal circuit and a portion of the silicide layer of the ESD protection device with a mask layer, etching the silicide layers uncovered by the mask layer to expose the conductive layer and a portion of the source/drain region, forming heavy P-type doped regions by ion implantation under the masking of the mask layer, and implementing another ion implantation to form an ESD implantation region under the entire drain region and enveloping the LDD structure. The heavy P-type ESD implantation region is located under a portion of the source/drain regions to form Zener junctions, which reduces the junction breakdown voltage. Moreover, the N-type ESD implantation avoids the ESD robustness degradation resulting from the LDD structure. However, the Zener junction formed by the P-type ESD implantation has a high leakage current and also increases the parasitic junction capacitance of the ESD protection device.
In mixed-voltage ICs, the core logic circuits operate at a low voltage level but the I/O circuits operate at a higher voltage level. The ESD implantation essential to the ESD protection device decreases the Zener junction breakdown voltage from 8V to 5V. As a result the ESD protection device becomes susceptible to faulty or unintentional triggered by noise or signal overshooting. In high-speed ICs, the parasitic junction capacitance of the ESD protection device is proportional to junction depletion depth. The P-type ESD implantation increases the junction capacitance of the Zener junction since the depletion width of the Zener junction in the ESD protection transistor is thinner than that of the device without the P-type implantation, which degrades the circuit speed of the I/O interface. Therefore, ESD protection devices with the P-type ESD implantation are not suitable for high-speed or mixed-voltage ICs.